Digital Fundamentals (11th Edition)
Verified Answer ✓
The output remains the same. ; In the given S-R ... more
Verified Answer ✓
; The inputs, S and R, are taken from the ... more
Verified Answer ✓
; The input is inverted in the given figure. ... more
Verified Answer ✓
The three different types of latches are as given ... more
Verified Answer ✓
; An active high S-R latch(SET-RESET) is formed ... more
Verified Answer ✓
; In the D-latch, when the EN and the D are high... more
Verified Answer ✓
; For a negative-edge triggering, the D input is ... more
Verified Answer ✓
; Positive edge triggering is used, when the ... more
Verified Answer ✓
; The D input of the waveform is taken as it is ... more
Verified Answer ✓
; In the given figure if and waveforms are ... more
Verified Answer ✓
; In the given figure if and waveforms are ... more
Verified Answer ✓
The Gated D latch changes its values at any time, ... more
Verified Answer ✓
The JK flip-flop depends on two inputs, whereas ... more
Verified Answer ✓
Output goes HIGH on the trailing edge of the ... more
Verified Answer ✓
Verified Answer ✓
The 74AHC74 CMOS flip-flop operates at the highest... more
Verified Answer ✓
5 flip-flops ; In a flip-flop, the frequency ... more
Verified Answer ✓
4 flip-flops required for 16 states. ; For the ... more
Verified Answer ✓
Register. ; A flip flop is a bistable ... more
Verified Answer ✓
; In order to perform divide by 2 operation, the ... more
Verified Answer ✓
; Use the relation to find number of flip flops n... more
Verified Answer ✓
; Use the relation to find external capacitance ... more
Verified Answer ✓
; Use the relation to find external resistance ... more
Verified Answer ✓
; Use the relation to find resistance for pulse ... more
Verified Answer ✓
Non retriggerable one shot times out whereas ... more
Verified Answer ✓
External R and C components are used to set the ... more
Verified Answer ✓
; Use the relation to find pulse width for ... more
Verified Answer ✓
; Use the relation to find the duty cycle for ... more
Verified Answer ✓
Astable multivibrator has no state in stable ... more
Verified Answer ✓
; Use the relation to find duty cycle for time ... more
Verified Answer ✓
Yes ; In place of negative edge-triggered D flip ... more
Verified Answer ✓
555 timer as an astable multivibrator ; There are ... more
Verified Answer ✓
; The pulse width of a 555 timer depends of the ... more
Verified Answer ✓
; The pulse width of a 555 timer depends of the ... more
Verified Answer ✓
The 24 MHz external clock is reduced to 1 Hz. ; ... more
Verified Answer ✓
; A variable, when ORed with its complement, is ... more
Verified Answer ✓
; The K-map is constructed with the given ... more
Verified Answer ✓
; The K-map is constructed with the given ... more
Verified Answer ✓
Yes ; The expression for obtained from the logic ... more
Verified Answer ✓
Latches are temporary storage devices, and they ... more
Verified Answer ✓
The latch is a bi-stable device. It stays at ... more
Verified Answer ✓
The output of the gated-D latch follows the input... more
Verified Answer ✓
Both the latches and the flip-flops are bi–stable ... more
Verified Answer ✓
The output of an edge-triggered flip-flop changes ... more
Verified Answer ✓
An edge triggered flip-flop changes at the ... more
Verified Answer ✓
An edge triggered J-K flip flop is said to be in ... more
Verified Answer ✓
One-shot is also known as a mono-stable multi-... more
Verified Answer ✓
One-shot is also known as a mono-stable multi-... more
Verified Answer ✓
The 555 time can be used as either a mono-stable ... more
Verified Answer ✓
When input S is 1 and R is 0, the output Q is HIGH... more
Verified Answer ✓
When input S is 1 and R is 0, the output Q is HIGH... more
Verified Answer ✓
When the EN (enable) pulse is LOW, the output ... more
Verified Answer ✓
Flip-flops are bi-stable devices and one of their ... more
Verified Answer ✓
To clear the flip-flop, CLR (clear) input is used... more
Verified Answer ✓
A change in the state of the output of this flip-... more
Verified Answer ✓
In the J-K flip-flop, when both inputs are HIGH, ... more
Verified Answer ✓
When J = 1 and K = 0, the J-K flip-flop is in the ... more
Verified Answer ✓
The output Q is constantly high, when input J = 1 ... more
Verified Answer ✓
A monostable multivibrator has one shot or one ... more
Verified Answer ✓
The output pulse width is not dependent on the ... more
Verified Answer ✓
An astable multivibrator has no stable state; it ... more
Verified Answer ✓
; An S-R latch consists of two inputs, S and R, ... more
Verified Answer ✓
; An S-R latch consists of two inputs, S and R, ... more
Verified Answer ✓
; An S-R latch consists of two inputs, S and R, ... more
Verified Answer ✓
; Draw the truth table for the S-R latch. The S-R... more
Verified Answer ✓
; The truth table giving the operation of the ... more
Verified Answer ✓
; The truth table giving the operation of the ... more
Verified Answer ✓
; The truth table giving the operation of the ... more
Verified Answer ✓
; A positive edge-triggered flip flop does not ... more
Verified Answer ✓
; A positive edge-triggered D flip flop changes ... more
Verified Answer ✓
; A positive edge-triggered D flip flop changes ... more
Verified Answer ✓
; The truth table for a positive edge-triggered ... more
Verified Answer ✓
; The truth table for a positive edge-triggered D... more
Verified Answer ✓
; The truth table for a positive edge-triggered D... more
Verified Answer ✓
; Draw the truth table for a positive edge-... more
Verified Answer ✓
; The truth table for a negative edge-triggered J... more
Verified Answer ✓
Inputs: J = 0010000 and K = 0000100Output: Q = ... more
Verified Answer ✓
; From the circuit, J and K, which are outputs of... more
Verified Answer ✓
; The inputs, J1, J2, and J3, are serially ... more
Verified Answer ✓
DC (direct current) supply voltage (VCC) and DC ... more
Verified Answer ✓
The following are the four propagation delay times... more
Verified Answer ✓
; To calculate the minimum time period, which is ... more
Verified Answer ✓
; Initially, the D flip flop is RESET, which ... more
Verified Answer ✓
; For the given condition, all the flip flops ... more
Verified Answer ✓
; To calculate the minimum time period of the ... more
Verified Answer ✓
This flip flop divides the clock by two and the ... more
Verified Answer ✓
The timing diagram of the circuit is shown below... more
Verified Answer ✓
; The output width can be found by multiplying ... more
Verified Answer ✓
; The general formula to calculate pulse width ... more
Verified Answer ✓
Use the standard value of .Thus, and . ; For the ... more
Verified Answer ✓
; The frequency of the output is determined by ... more
Verified Answer ✓
; The duty cycle of 555 timer configured to run ... more
Verified Answer ✓
Verified Answer ✓
Verified Answer ✓
The flip-flop is not working correctly because it ... more
Verified Answer ✓
The clear input is shorted to the ground. ; It is... more
Verified Answer ✓
Verified Answer ✓
Verified Answer ✓
The pulse width of the left side's 74121 one-shot ... more
Verified Answer ✓
The circuit in Figure-1 is same for both timer ... more
Verified Answer ✓
The circuit is same for both timer and timer, ... more
Verified Answer ✓
The circuit in Figure-1 is same for both timer ... more
Verified Answer ✓
; The traffic controller have three color signals... more
Verified Answer ✓
In the timing circuit unit of the traffic signal ... more
Verified Answer ✓
; To produce the sequence from zero to seven, so ... more
Verified Answer ✓
; Since each box's capacity is 32, after ... more
Verified Answer ✓
The modified state diagram is shown in figure ... more